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d a t a sh eet product speci?cation supersedes data of 1998 may 12 file under integrated circuits, ic02 1999 jul 13 integrated circuits tda4853; tda4854 i 2 c-bus autosync deflection controllers for pc/tv monitors
1999 jul 13 2 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 features concept features full horizontal plus vertical autosync capability; tv and vcr mode included extended horizontal frequency range from 15 to 130 khz comprehensive set of i 2 c-bus driven geometry adjustments and functions, including standby mode very good vertical linearity moire cancellation start-up and switch-off sequence for safe operation of all power components x-ray protection flexible switched mode b+ supply function block for feedback and feed forward converter internally stabilized voltage reference drive signal for focus amplifiers with combined horizontal and vertical parabola waveforms (tda4854) dc controllable inputs for extremely high tension (eht) compensation sdip32 package. synchronization can handle all sync signals (horizontal, vertical, composite and sync-on-video) output for video clamping (leading/trailing edge selectable by i 2 c-bus), vertical blanking and protection blanking output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube. horizontal section i 2 c-bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase frequency-locked loop for smooth catching of horizontal frequency tv mode at 15.625 or 15.750 khz selectable by i 2 c-bus simple frequency preset of f min and f max by external resistors low jitter soft start for horizontal and b+ control drive signals. vertical section i 2 c-bus controllable vertical picture size, picture position, linearity (s-correction) and linearity balance output for i 2 c-bus controllable vertical sawtooth and parabola (for pin unbalance and parallelogram) vertical picture size independent of frequency differential current outputs for dc coupling to vertical booster 50 to 160 hz vertical autosync range. east-west (ew) section i 2 c-bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction optional tracking of ew drive waveform with line frequency selectable by i 2 c-bus. focus section of tda4854 i 2 c-bus controllable output for horizontal and vertical parabolas vertical parabola is independent of frequency and tracks with vertical adjustments horizontal parabola independent of frequency pre-correction of delay in focus output stage.
1999 jul 13 3 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 general description the tda4854 is a high performance and efficient solution for autosync monitors. all functions are controllable by i 2 c-bus. the tda4854 provides synchronization processing, horizontal and vertical synchronization with full autosync capability, a tv/vcr mode and very short settling times after mode changes. external power components are given a great deal of protection. the ic generates the drive waveforms for dc-coupled vertical boosters such as the tda486x and tda835x. the tda4854 provides extended functions e.g. as a flexible b+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals. the tda4853 is an economy version of the tda4854, especially designed for use in 14 and 15 monitors with combined eht generation. it provides the same features as the tda4854 except for the dynamic focus block. together with the i 2 c-bus driven philips tda488x video processor family, a very advanced system solution is offered. quick reference data ordering information symbol parameter min. typ. max. unit v cc supply voltage 9.2 - 16 v i cc supply current - 70 - ma i cc(stb) supply current during standby mode - 9 - ma vsize vertical size 60 - 100 % vga vga overscan for vertical size - 16.8 - % vpos vertical position - 11.5 - % vlin vertical linearity (s-correction) - 2 -- 46 % vlinbal vertical linearity balance - 2.5 - % v hsize horizontal size voltage 0.13 - 3.6 v v hpin horizontal pincushion voltage (ew parabola) 0.04 - 1.42 v v heht horizontal size modulation voltage 0.02 - 0.69 v v htrap horizontal trapezium correction voltage - 0.33 - v v hcor horizontal corner correction voltage - 0.64 - +0.08 v hpos horizontal position - 13 - % hparal horizontal parallelogram - 1 - % hpinbal ew pin unbalance - 1 - % t amb operating ambient temperature - 20 - +70 c type number package name description version tda4853 sdip32 plastic shrink dual in-line package; 32 leads (400 mil) sot232-1 tda4854 sdip32 plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
1999 jul 13 4 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagrams o ok, full pagewidth vertical sync input and polarity correction vertical sync integrator vertical oscillator and agc ew-output horizontal pincushion horizontal corner horizontal trapezium horizontal size vertical linearity vertical linearity balance horizontal size and vertical size eht compensation output asymmetric ew-correction i 2 c-bus receiver hunlock output vertical position vertical size, vovscn video clamping and vertical blank supply and reference horizontal oscillator pll1 and horizontal position pll2, parallelogram, pin unbalance and soft start coincidence detector frequency detector tv mode i 2 c-bus registers protection and soft start x-ray protection horizontal output stage b + control 22 k w 3.3 k w 100 nf 8.2 nf 150 nf (1%) x-ray 10 nf r hbuf (2%) r href (1%) (1) b + control application (2) (ttl level) (ttl level) 9.2 to 16 v i.c. (video) clamping blanking 14 23 22 21 31 11 100 nf (5%) 24 vout2 12 vout1 ascor 13 bdrv bsens bop bin 8 hdrv or 20 17 19 18 6 4 3 5 10 7 32 25 16 15 26 27 28 29 8.2 nf 30 1 tda4853 h/c sync input and polarity correction mgm101 2 9 vertical output sda scl hsync sgnd pgnd clbl vsync v cc ewdrv vsmod vagc vcap vref hsmod 7 v 1.2 v eht compensation via horizontal size eht compensation via vertical size hflb hpll2 hcap href hbuf hpll1 xray xsel hunlock fig.1 block diagram and application circuit of tda4853. (1) for the calculation of f h range see section calculation of line frequency range. (2) see figs 23 and 24.
1999 jul 13 5 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... o ok, full pagewidth vertical sync input and polarity correction vertical sync integrator vertical oscillator and agc ew-output horizontal pincushion horizontal corner horizontal trapezium horizontal size vertical linearity vertical linearity balance horizontal size and vertical size eht compensation output asymmetric ew-correction horizontal and vertical i 2 c-bus receiver hunlock output vertical position vertical size, vovscn video clamping and vertical blank supply and reference horizontal oscillator pll1 and horizontal position pll2, parallelogram, pin unbalance and soft start coincidence detector frequency detector tv mode i 2 c-bus registers protection and soft start x-ray protection horizontal output stage b + control 22 k w 3.3 k w 100 nf 8.2 nf 150 nf (1%) x-ray 10 nf r hbuf (2%) r href (1%) (1) b + control application (2) (ttl level) (ttl level) 9.2 to 16 v (video) clamping blanking 14 23 22 21 31 11 100 nf (5%) 24 vout2 12 vout1 ascor 13 32 focus bdrv bsens bop bin 8 hdrv or 20 17 19 18 6 4 3 5 10 7 25 16 15 26 27 28 29 8.2 nf 30 1 tda4854 h/c sync input and polarity correction mgm065 2 9 vertical output focus sda scl hsync sgnd pgnd clbl vsync v cc ewdrv vsmod vagc vcap vref hsmod 7 v 1.2 v eht compensation via horizontal size eht compensation via vertical size hflb hpll2 hcap href hbuf hpll1 xsel xray hunlock fig.2 block diagram and application circuit of tda4854. (1) for the calculation of f h range see section calculation of line frequency range. (2) see figs 23 and 24.
1999 jul 13 6 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 pinning note 1. external connections to this pin are not allowed. symbol pin description hflb 1 horizontal ?yback input xray 2 x-ray protection input bop 3 b+ control ota output bsens 4 b+ control comparator input bin 5 b+ control ota input bdrv 6 b+ control driver output pgnd 7 power ground hdrv 8 horizontal driver output xsel 9 select input for x-ray reset v cc 10 supply voltage ewdrv 11 ew waveform output vout2 12 vertical output 2 (ascending sawtooth) vout1 13 vertical output 1 (descending sawtooth) vsync 14 vertical synchronization input hsync 15 horizontal/composite synchronization input clbl 16 video clamping pulse/vertical blanking output hunlock 17 horizontal synchronization unlock/protection/vertical blanking output scl 18 i 2 c-bus clock input sda 19 i 2 c-bus data input/output ascor 20 output for asymmetric ew corrections vsmod 21 input for eht compensation (via vertical size) vagc 22 external capacitor for vertical amplitude control vref 23 external resistor for vertical oscillator vcap 24 external capacitor for vertical oscillator sgnd 25 signal ground hpll1 26 external ?lter for pll1 hbuf 27 buffered f/v voltage output href 28 reference current for horizontal oscillator hcap 29 external capacitor for horizontal oscillator hpll2 30 external ?lter for pll2/soft start hsmod 31 input for eht compensation (via horizontal size) i.c. 32 internally connected; note 1: tda4853 focus 32 output for horizontal and vertical focus: tda4854
1999 jul 13 7 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 fig.3 pin configuration for tda4853. handbook, halfpage tda4853 mgm066 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 hflb xray bop bsens bin bdrv pgnd hdrv xsel v cc ewdrv vout2 vout1 vsync i.c. hsmod hpll2 hcap hbuf hpll1 href sgnd vcap vref vagc vsmod ascor sda hsync clbl scl hunlock fig.4 pin configuration for tda4854. handbook, halfpage tda4854 mgm067 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 hflb xray bop bsens bin bdrv pgnd hdrv xsel v cc ewdrv vout2 vout1 vsync focus hsmod hpll2 hcap hbuf hpll1 href sgnd vcap vref vagc vsmod ascor sda hsync clbl scl hunlock functional description horizontal sync separator and polarity correction hsync (pin 15) is the input for horizontal synchronization signals, which can be dc-coupled ttl signals (horizontal or composite sync) and ac-coupled negative-going video sync signals. video syncs are clamped to 1.28 v and sliced at 1.4 v. this results in a fixed absolute slicing level of 120 mv related to top sync. for dc-coupled ttl signals the input clamping current is limited. the slicing level for ttl signals is 1.4 v. the separated sync signal (either video or ttl) is integrated on an internal capacitor to detect and normalize the sync polarity. normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the pll1 phase detector and the frequency-locked loop. the presence of equalization pulses is allowed for correct function of the pll1 phase detector only in tv mode. vertical sync integrator normalized composite sync signals from hsync are integrated on an internal capacitor in order to extract vertical sync pulses. the integration time is dependent on the horizontal oscillator reference current at href (pin 28). the integrator output directly triggers the vertical oscillator. vertical sync slicer and polarity correction vertical sync signals (ttl) applied to vsync (pin 14) are sliced at 1.4 v. the output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity. the output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator.
1999 jul 13 8 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 video clamping/vertical blanking generator the video clamping/vertical blanking signal at clbl (pin 16) is a two-level sandcastle pulse which is especially suitable for video ics such as the tda488x family, but also for direct applications in video output stages. the upper level is the video clamping pulse, which is triggered by the horizontal sync pulse. either the leading or trailing edge can be selected by setting control bit clamp via the i 2 c-bus. the width of the video clamping pulse is determined by an internal single-shot multivibrator. the lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. it is started by the vertical sync and stopped with the start of the vertical scan. this results in optimum vertical blanking. two different vertical blanking times are accessible, by control bit vblk, via the i 2 c-bus. blanking will be activated continuously if one of the following conditions is true: soft start of horizontal and b+ drive [voltage at hpll2 (pin 30) pulled down externally or by the i 2 c-bus] pll1 is unlocked while frequency-locked loop is in search mode or if horizontal sync pulses are absent no horizontal flyback pulses at hflb (pin 1) x-ray protection is activated supply voltage at v cc (pin 10) is low (see fig.25). horizontal unlock blanking can be switched off, by control bit blkdis, via the i 2 c-bus while vertical blanking and protection blanking is maintained. frequency-locked loop the frequency-locked loop can lock the horizontal oscillator over a wide frequency range. this is achieved by a combined search and pll operation. the frequency range is preset by two external resistors and the recommended maximum ratio is this can, for instance, be a range from 15.625 to 90 khz with all tolerances included. without a horizontal sync signal the oscillator will be free-running at f min . any change of sync conditions is detected by the internal coincidence detector. a deviation of more than 4% between horizontal sync and oscillator frequency will switch the horizontal section into search mode. this means that pll1 control currents are switched off immediately. the internal frequency detector then starts tuning the oscillator. very small dc currents at hpll1 (pin 26) are used to perform this tuning with a well defined change rate. when coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. the soft-lock mode is then replaced by a normal pll operation. this operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching. in this concept it is not allowed to load hpll1. the frequency dependent voltage at this pin is fed internally to hbuf (pin 27) via a sample-and-hold and buffer stage. the sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. an external resistor connected between pins hbuf and href defines the frequency range. out-of-lock indication (pin hunlock) pin hunlock is floating during search mode if no sync pulses are applied, or if a protection condition is true. all this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage. for an additional fast vertical blanking at grid 1 of the picture tube a 1 v signal referenced to ground is available at this output. the continuous protection blanking (see section video clamping/vertical blanking generator) is also available at this pin. horizontal unlock blanking can be switched off, by control bit blkdis via the i 2 c-bus while vertical blanking is maintained. tv mode in applications with tv signals the standard frequency-to-voltage converter operation will be disturbed by equalizing sync pulses and phase jumps occurring in vcr signals. to avoid this, a tv mode has been implemented. it can be accessed by choosing the horizontal tv sync frequencies of 15.625 or 15.75 khz as the minimum frequency for the horizontal oscillator. applying tv signals will cause the frequency-to-voltage converter to scan down to this frequency in normal operation. if the control bit tvmod is sent by the i 2 c-bus, the hbuf output is clamped to 2.5 v and an internally defined pll1 control range of 10% is established. to return to standard operation of the frequency-to-voltage converter the bit tvmod has to be reset. for an optimal operation with vcr signals the rc combination at pin hpll1 has to be switched externally. f max f min --------- - 6.5 1 ------- - =
1999 jul 13 9 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 horizontal oscillator the horizontal oscillator is of the relaxation type and requires a capacitor of 10 nf to be connected at hcap (pin 29). for optimum jitter performance the value of 10 nf must not be changed. the minimum oscillator frequency is determined by a resistor connected between pin href and ground. a resistor connected between pins href and hbuf defines the frequency range. the reference current at pin href also defines the integration time constant of the vertical sync integration. calculation of line frequency range the oscillator frequencies f min and f max must first be calculated. this is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies f sync(min) and f sync(max) . the oscillator is driven by the currents in r href and r hbuf . the following example is a 31.45 to 90 khz application: table 1 calculation of total spread thus the typical frequency range of the oscillator in this example is: the tv mode is centred around f min with a control range of 10%. activation of the tv mode is only allowed between 15.625 and 35 khz. the resistors r href and r hbufpar can be calculated using the following formulae: the resistor r hbufpar is calculated as the value of r href and r hbuf in parallel. the formulae for r hbuf also takes into account the voltage swing across this resistor pll1 phase detector the phase detector is a standard type using switched current sources, which are independent of the horizontal frequency. it compares the middle of the horizontal sync with a fixed point on the oscillator sawtooth voltage. the pll1 loop filter is connected to hpll1 (pin 26). see also section horizontal position adjustment and corrections. horizontal position adjustment and corrections a linear adjustment of the relative phase between the horizontal sync and the oscillator sawtooth (in pll1 loop) is achieved via register hpos. once adjusted, the relative phase remains constant over the whole frequency range. correction of pin unbalance and parallelogram is achieved by modulating the phase between the oscillator sawtooth and horizontal flyback (in loop pll2) via registers hparal and hpinbal. if those asymmetric ew corrections are performed in the deflection stage, both registers can be disconnected from the horizontal phase via control bit acd. this does not change the output at pin ascor. horizontal moire cancellation to achieve a cancellation of horizontal moire (also known as video moire), the horizontal frequency is divided-by-two to achieve a modulation of the horizontal phase via pll2. the amplitude is controlled by register hmoire. to avoid a visible structure on screen the polarity changes with half of the vertical frequency. control bit mod disables the moire cancellation function. spread of for f max for f min ic 3% 5% c hcap 2% 2% r href , r hbuf 2% 2% total 7% 9% f max f sync max () 1.07 96.3 khz == f min f sync min () 1.09 ---------------------- - 28.9 khz == r href 78 khz k w f min 0.0012 f min 2 + khz [] ----------------------------------------------------------------- 2.61 k w == r hbufpar 78 khz k w f max 0.0012 f max 2 + khz [] ------------------------------------------------------------------- - 726 w == r hbuf r href r hbufpar r href r hbufpar C --------------------------------------------- - 0.8 = 805 w =
1999 jul 13 10 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 pll2 phase detector the pll2 phase detector is similar to the pll1 detector and compares the line flyback pulse at hflb (pin 1) with the oscillator sawtooth voltage. the control currents are independent of the horizontal frequency. the pll2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the hdrv (pin 8) output pulse. for the tda4854 external modulation of the pll2 phase is not allowed, because this would disturb the start advance of the horizontal focus parabola. soft start and standby if hpll2 is pulled to ground by resetting the register softst, the horizontal output pulses, vertical output currents and b+ control driver pulses will be inhibited. this means that hdrv (pin 8), bdrv (pin 6), vout1 (pin 13) and vout2 (pin 12) are floating in this state. if hpll2 is pulled to ground by an external dc current, vertical output currents stay active while hdrv (pin 8) and bdrv (pin 6) are in floating state. in both cases the pll2 and the frequency-locked loop are disabled, clbl (pin 16) provides a continuous blanking signal and hunlock (pin 17) is floating. this option can be used for soft start, protection and power-down modes. when the hpll2 pin is released again, an automatic soft start sequence on the horizontal drive as well as on the b+ drive output will be performed (see figs 26 and 27). a soft start can only be performed if the supply voltage for the ic is a minimum of 8.6 v. the soft start timing is determined by the filter capacitor at hpll2 (pin 30), which is charged with a constant current during soft start. if the voltage at pin 30 (hpll2) reaches 1.1 v, the vertical output currents are enabled. at 1.7 v the horizontal driver stage generates very small output pulses. the width of these pulses increases with the voltage at hpll2 until the final duty cycle is reached. the voltage at hpll2 increases further and performs a soft start at bdrv (pin 6) as well. the voltage at hpll2 continues to rise until hpll2 enters its normal operating range. the internal charge current is now disabled. finally pll2 and the frequency-locked loop are activated. if both functions reach normal operation, hunlock (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at clbl (pin 16) is removed. output stage for line drive pulses [hdrv (pin 8)] an open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 v at 20 ma. to protect the line deflection transistor, the output stage is disabled (floating) for a low supply voltage at v cc (see fig.25). the duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. this ensures optimum drive conditions over the whole frequency range. x-ray protection the x-ray protection input xray (pin 2) provides a voltage detector with a precise threshold. if the input voltage at xray exceeds this threshold for a certain time then control bit softst is reset, which switches the ic into protection mode. in this mode several pins are forced into defined states: hunlock (pin 17) is floating the capacitor connected to hpll2 (pin 30) is discharged horizontal output stage (hdrv) is floating b+ control driver stage (bdrv) is floating vertical output stages (vout1 and vout2) are floating clbl provides a continuous blanking signal. there are two different methods of restarting the ic: 1. xsel (pin 9) is open-circuit or connected to ground. the control bit softst must be set to logic 1 via the i 2 c-bus. the ic then returns to normal operation via soft start. 2. xsel (pin 9) is connected to v cc via an external resistor. the supply voltage of the ic must be switched off for a certain period of time before the ic can be restarted again using the standard power-on procedure.
1999 jul 13 11 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 vertical oscillator and amplitude control this stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. the free-running frequency f fr(v) is determined by the resistor r vref connected to pin 23 and the capacitor c vcap connected to pin 24. the value of r vref is not only optimized for noise and linearity performance in the whole vertical and ew section, but also influences several internal references. therefore the value of r vref must not be changed. capacitor c vcap should be used to select the free-running frequency of the vertical oscillator in accordance with the following formula: to achieve a stabilized amplitude the free-running frequency f fr(v) , without adjustment, should be at least 10% lower than the minimum trigger frequency. the contributions shown in table 2 can be assumed. table 2 calculation of f fr(v) total spread result for 50 to 160 hz application: the agc of the vertical oscillator can be disabled by setting control bit agcdis via the i 2 c-bus. a precise external current has to be injected into vcap (pin 24) to obtain the correct vertical size. this special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 hz up converter for video signals. application hint : vagc (pin 22) has a high input impedance during scan. therefore, the pin must not be loaded externally otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan. adjustment of vertical size, vga overscan and eht compensation the amplitude of the differential output currents at vout1 and vout2 can be adjusted via register vsize. register vovscn can activate a +17% step in vertical size for the vga350 mode. vsmod (pin 21) can be used for a dc controlled eht compensation of vertical size by correcting the differential output currents at vout1 and vout2. the ew waveforms, (vertical focus), pin unbalance and parallelogram corrections are not affected by vsmod. the adjustments for vertical size and vertical position also affect the waveforms of the horizontal pincushion, vertical linearity (s-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. the result of this interaction is that no re-adjustment of these parameters is necessary after an adjustment of vertical picture size or position. adjustment of vertical position, vertical linearity and vertical linearity balance register vpos provides a dc shift at the sawtooth outputs vout1 and vout2 (pins 13 and 12) and the ew drive output ewdrv (pin 11) in such a way that the whole picture moves vertically while maintaining the correct geometry. register vlin is used to adjust the amount of vertical s-correction in the output signal. this function can be switched off by control bit vsc. register vlinbal is used to correct the unbalance of the vertical s-correction in the output signal. this function can be switched off by control bit vlc. adjustment of vertical moire cancellation to achieve a cancellation of vertical moire (also known as scan moire) the vertical picture position can be modulated by half the vertical frequency. the amplitude of the modulation is controlled by register vmoire and can be switched off via control bit mod. contributing elements minimum frequency offset between f fr(v) and lowest trigger frequency 10% spread of ic 3% spread of r vref 1% spread of c vcap 5% total 19% f fr v () 1 10.8 r vref c vcap ----------------------------------------------------------- = f fr v () 50 hz 1.19 --------------- 42 hz ==
1999 jul 13 12 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 horizontal pincushion (including horizontal size, corner correction and trapezium correction) ewdrv (pin 11) provides a complete ew drive waveform. the components horizontal pincushion, horizontal size, corner correction and trapezium correction are controlled by the registers hpin, hsize, hcor and htrap. htrap can be set to zero by control bit vpc. the pincushion (ew parabola) amplitude, corner and trapezium correction track with the vertical picture size (vsize) and also with the adjustment for vertical picture position (vpos). the corner correction does not track with the horizontal pincushion (hpin). further the horizontal pincushion amplitude, corner and trapezium correction track with the horizontal picture size, which is adjusted via register hsize and the analog modulation input hsmod. if the dc component in the ewdrv output signal is increased via hsize or i hsmod , the pincushion, corner and trapezium component of the ewdrv output will be reduced by a factor of the value 14.4 v is a virtual voltage for calculation only. the output pin can not reach this value, but the gain (and dc bias) of the external application should be such that the horizontal deflection is reduced to zero when ewdrv reaches 14.4 v. hsmod can be used for a dc controlled eht compensation by correcting horizontal size, horizontal pincushion, corner and trapezium. the control range at this pin tracks with the actual value of hsize. for an increasing dc component v hsize in the ewdrv output signal, the dc component v heht caused by i hsmod will be reduced by a factor of as shown in the equation above. the whole ewdrv voltage is calculated as follows: v ewdrv = 1.2 v + [v hsize +v heht f(hsize) + (v hpin + v hcor +v htrap ) g(hsize, hsmod)] h(i href ) where: two different modes of operation can be chosen for the ew output waveform via control bit fhmult: 1. mode 1 horizontal size is controlled via register hsize and causes a dc shift at the ewdrv output. the complete waveform is also multiplied internally by a signal proportional to the line frequency [which is detected via the current at href (pin 28)]. this mode is to be used for driving ew diode modulator stages which require a voltage proportional to the line frequency. 2. mode 2 the ew drive waveform does not track with the line frequency. this mode is to be used for driving ew modulators which require a voltage independent of the line frequency. output stage for asymmetric correction waveforms [ascor (pin 20)] this output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth. the amplitude and polarity of both signals can be changed via registers hparal and hpinbal. application hint : the tda4854 offers two possibilities to control registers hpinbal and hparal. 1. control bit acd = 1 the two registers now control the horizontal phase by means of internal modulation of the pll2 horizontal phase control. the ascor output (pin 20) can be left unused, but it will always provide an output signal because the ascor output stage is not influenced by the control bit acd. 2. control bit acd = 0 the internal modulation via pll2 is disconnected. in order to obtain the required effect on the screen, pin ascor must now be fed to the dc amplifier which controls the dc shift of the horizontal deflection. this option is useful for applications which already use a dc shift transformer. if the tube does not need hpinbal and hparal, then pin ascor can be used for other purposes, i.e. for a simple dynamic convergence. 1 v hsize v heht 1 v hsize 14.4 v ----------------- C ? ?? + 14.4 ------------------------------------------------------------------------ - C 1 v hsize 14.4 v ---------------- - C v heht i hsmod 120 m a ------------------- - 0.69 = f(hsize) 1 v hsize 14.4 v ----------------- C = g(hsize, hsmod) 1 v hsize v heht 1 v hsize 14.4 v ----------------- C ? ?? + 14.4 v -------------------------------------------------------------------------- C = hi href () i href i href f70khz = ------------------------------- - =
1999 jul 13 13 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 tda4854: dynamic focus section [focus (pin 32)] this section generates a complete drive signal for dynamic focus applications. the amplitude of the horizontal parabola is internally stabilized, thus it is independent of the horizontal frequency. the amplitude can be adjusted via register hfocus. changing horizontal size may require a correction of hfocus. to compensate for the delay in external focus amplifiers a pre-correction for the phase of the horizontal parabola has been implemented. the amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments. the amplitude can be adjusted via register vfocus. focus (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas. b+ control function block the b+ control function block of the tda4853; tda4854 consists of an operational transconductance amplifier (ota), a voltage comparator, a flip-flop and a discharge circuit. this configuration allows easy applications for different b+ control concepts. see also application note an96052: b+ converter topologies for horizontal deflection and eht with tda4855/58 . g eneral description the non-inverting input of the ota is connected internally to a high precision reference voltage. the inverting input is connected to bin (pin 5). an internal clamping circuit limits the maximum positive output voltage of the ota. the output itself is connected to bop (pin 3) and to the inverting input of the voltage comparator. the non-inverting input of the voltage comparator can be accessed via bsens (pin 4). b+ drive pulses are generated by an internal flip-flop and fed to bdrv (pin 6) via an open-collector output stage. this flip-flop is set at the rising edge of the signal at hdrv (pin 8). the falling edge of the output signal at bdrv has a defined delay of t d(bdrv) to the rising edge of the hdrv pulse (see fig.23). when the voltage at bsens exceeds the voltage at bop, the voltage comparator output resets the flip-flop and, therefore, the open-collector stage at bdrv is floating again. an internal discharge circuit allows a well defined discharge of capacitors at bsens. bdrv is active at a low-level output voltage (see figs 23 and 24), thus it requires an external inverting driver stage. the b+ function block can be used for b+ deflection modulators in many different ways. two popular application combinations are as follows: boost converter in feedback mode (see fig.23) in this application the ota is used as an error amplifier with a limited output voltage range. the flip-flop is set on the rising edge of the signal at hdrv. a reset will be generated when the voltage at bsens, taken from the current sense resistor, exceeds the voltage at bop. if no reset is generated within a line period. the rising edge of the next hdrv pulse forces the flip-flop to reset. the flip-flop is set immediately after the voltage at bsens has dropped below the threshold voltage v restart(bsens) . buck converter in feed forward mode (see fig.24) this application uses an external rc combination at bsens to provide a pulse width which is independent from the horizontal frequency. the capacitor is charged via an external resistor and discharged by the internal discharge circuit. for normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. the capacitor will now be discharged with a constant current until the internally controlled stop level v stop(bsens) is reached. this level will be maintained until the rising edge of the next hdrv pulse sets the flip-flop again and disables the discharge circuit. if no reset is generated within a line period, the rising edge of the next hdrv pulse automatically starts the discharge sequence and resets the flip-flop. when the voltage at bsens reaches the threshold voltage v restart(bsens) , the discharge circuit will be disabled automatically and the flip-flop will be set immediately. this behaviour allows a definition of the maximum duty cycle of the b+ control drive pulse by the relationship of charge current to discharge current. supply voltage stabilizer, references, start-up procedures and protection functions the tda4853; tda4854 provides an internal supply voltage stabilizer for excellent stabilization of all internal references. an internal gap reference, especially designed for low-noise, is the reference for the internal horizontal and vertical supply voltages. all internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors. if either the supply voltage is below 8.3 v or no data from the i 2 c-bus has been received after power-up, the internal soft start and protection functions do not allow any of those outputs [hdrv, bdrv, vout1, vout2 and hunlock (see fig.25)] to be active.
1999 jul 13 14 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 for supply voltages below 8.3 v the internal i 2 c-bus will not generate an acknowledge and the ic is in standby mode. this is because the internal protection circuit has generated a reset signal for the soft start register softst. above 8.3 v data is accepted and all registers can be loaded. if the register softst has received a set from the i 2 c-bus, the internal soft start procedure is released, which activates all mentioned outputs. if during normal operation the supply voltage has dropped below 8.1 v, the protection mode is activated and hunlock (pin 17) changes to the protection status and is floating. this can be detected by the microcontroller. this protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. this protection mode can be activated as shown in table 3. table 3 activation of protection mode when the protection mode is active, several pins of the tda4853; tda4854 are forced into a defined state: hdrv (horizontal driver output) is floating bdrv (b+ control driver output) is floating hunlock (indicates, that the frequency-to-voltage converter is out of lock) is floating (high via external pull-up resistor) clbl provides a continuous blanking signal vout1 and vout2 (vertical outputs) are floating the capacitor at hpll2 is discharged. if the soft start procedure is activated via the i 2 c-bus, all of these actions will be performed in a well defined sequence (see figs 25 and 26). activation reset low supply voltage at pin 10 increase supply voltage; reload registers; soft start via i 2 c-bus power dip, below 8.1 v reload registers; soft start via i 2 c-bus x-ray protection (pin 2) triggered, xsel (pin 9) is open-circuit or connected to ground reload registers; soft start via i 2 c-bus x-ray protection (pin 2) triggered, xsel (pin 9) connected to v cc via an external resistor switch v cc off and on again, reload registers; soft start via i 2 c-bus hpll2 (pin 30) externally pulled to ground release pin 30
1999 jul 13 15 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 limiting values in accordance with the absolute maximum rating system (iec 134); all voltages measured with respect to ground. notes 1. machine model: 200 pf; 0.75 m h; 10 w . 2. human body model: 100 pf; 7.5 m h; 1500 w . thermal characteristics quality specification in accordance with urf-4-2-59/601 ; emc emission/immunity test in accordance with dis 1000 4.6 (iec 801.6). note 1. tests are performed with application reference board. tests with other boards will have different results. symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +16 v v i(n) input voltage for pins: bin - 0.5 +6.0 v hsync, vsync, vref, href, vsmod and hsmod - 0.5 +6.5 v sda and scl - 0.5 +8.0 v xray - 0.5 +8.0 v v o(n) output voltage for pins: vout2, vout1 and hunlock - 0.5 +6.5 v bdrv and hdrv - 0.5 +16 v v i/o(n) input/output voltages at pins bop and bsens - 0.5 +6.0 v i o(hdrv) horizontal driver output current - 100 ma i i(hflb) horizontal ?yback input current - 10 +10 ma i o(clbl) video clamping pulse/vertical blanking output current -- 10 ma i o(bop) b+ control ota output current - 1ma i o(bdrv) b+ control driver output current - 50 ma i o(ewdrv) ew driver output current -- 5ma i o(focus) focus driver output current -- 5ma t amb operating ambient temperature - 20 +70 c t j junction temperature - 150 c t stg storage temperature - 55 +150 c v esd electrostatic discharge for all pins note 1 - 150 +150 v note 2 - 2000 +2000 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 55 k/w symbol parameter conditions min. typ. max. unit v emc emission test note 1 - 1.5 - mv immunity test note 1 - 2.0 - v
1999 jul 13 16 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 characteristics v cc = 12 v; t amb =25 c; peripheral components in accordance with figs 1 and 2; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit horizontal sync separator i nput characteristics for dc- coupled ttl signals : pin hsync v i(hsync) sync input signal voltage 1.7 -- v v hsync(sl) slicing voltage level 1.2 1.4 1.6 v t r(hsync) rise time of sync pulse 10 - 500 ns t f(hsync) fall time of sync pulse 10 - 500 ns t w(hsync)(min) minimum width of sync pulse 0.7 --m s i i(hsync) input current v hsync = 0.8 v --- 200 m a v hsync = 5.5 v -- 10 m a i nput characteristics for ac- coupled video signals ( sync - on - video , negative sync polarity ) v hsync sync amplitude of video input signal voltage r source =50 w- 300 - mv v hsync(sl) slicing voltage level (measured from top sync) r source =50 w 90 120 150 mv v clamp(hsync) top sync clamping voltage level r source =50 w 1.1 1.28 1.5 v i ch(hsync) charge current for coupling capacitor v hsync >v clamp(hsync) 1.7 2.4 3.4 m a t w(hsync)(min) minimum width of sync pulse 0.7 --m s r source(max) maximum source resistance duty cycle = 7% -- 1500 w r i(diff)(hsync) differential input resistance during sync - 80 -w automatic polarity correction for horizontal sync horizontal sync pulse width related to line period -- 25 % t d(hpol) delay time for changing polarity 0.3 - 1.8 ms vertical sync integrator t int(v) integration time for generation of a vertical trigger pulse f h = 15.625 khz; i href = 0.52 ma 14 20 26 m s f h = 31.45 khz; i href = 1.052 ma 71013 m s f h = 64 khz; i href = 2.141 ma 3.9 5.7 6.5 m s f h = 100 khz; i href = 3.345 ma 2.5 3.8 4.5 m s vertical sync slicer (dc-coupled, ttl compatible): pin vsync v i(vsync) sync input signal voltage 1.7 -- v v vsync(sl) slicing voltage level 1.2 1.4 1.6 v i i(vsync) input current 0 v < v sync < 5.5 v -- 10 m a t ph () t h ----------- -
1999 jul 13 17 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 automatic polarity correction for vertical sync t w(vsync)(max) maximum width of vertical sync pulse -- 400 m s t d(vpol) delay time for changing polarity 0.45 - 1.8 ms video clamping/vertical blanking output: pin clbl t clamp(clbl) width of video clamping pulse measured at v clbl = 3 v 0.6 0.7 0.8 m s v clamp(clbl) top voltage level of video clamping pulse 4.32 4.75 5.23 v tc clamp temperature coef?cient of v clamp(clbl) - 4 - mv/k stps clamp steepness of slopes for clamping pulse r l =1m w ; c l =20pf - 50 - ns/v t d(hsynct-clbl) delay between trailing edge of horizontal sync and start of video clamping pulse clamping pulse triggered on trailing edge of horizontal sync; control bit clamp = 0; measured at v clbl =3v - 130 - ns t clamp1(max) maximum duration of video clamping pulse referenced to end of horizontal sync -- 1.0 m s t d(hsyncl-clbl) delay between leading edge of horizontal sync and start of video clamping pulse clamping pulse triggered on leading edge of horizontal sync; control bit clamp = 1; measured at v clbl =3v - 300 - ns t clamp2(max) maximum duration of video clamping pulse referenced to end of horizontal sync -- 0.15 m s v blank(clbl) top voltage level of vertical blanking pulse notes 1 and 2 1.7 1.9 2.1 v t blank(clbl) width of vertical blanking pulse at pins clbl and hunlock control bit vblk = 0 220 260 300 m s control bit vblk = 1 305 350 395 m s tc blank temperature coef?cient of v blank(clbl) - 2 - mv/k v scan(clbl) output voltage during vertical scan i clbl = 0 0.59 0.63 0.67 v tc scan temperature coef?cient of v scan(clbl) -- 2 - mv/k i sink(clbl) internal sink current 2.4 -- ma i l(clbl) external load current --- 3.0 ma symbol parameter conditions min. typ. max. unit
1999 jul 13 18 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 horizontal oscillator: pins hcap and href f fr(h) free-running frequency without pll1 action (for testing only) r hbuf = ; r href = 2.4 k w ; c hcap = 10 nf; note 3 30.53 31.45 32.39 khz d f fr(h) spread of free-running frequency (excluding spread of external components) -- 3.0 % tc fr temperature coef?cient of free-running frequency - 100 0 +100 10 - 6 /k f h(max) maximum oscillator frequency -- 130 khz v href voltage at input for reference current 2.43 2.55 2.68 v unlock blanking detection: pin hunlock v scan(hunlock) low level voltage of hunlock saturation voltage in case of locked pll1; internal sink current = 1 ma -- 250 mv v blank(hunlock) blanking level of hunlock external load current = 0 0.9 1 1.1 v tc blank temperature coef?cient of v blank(hunlock) -- 0.9 - mv/k tc sink temperature coef?cient of i sink(hunlock) - 0.15 - %/k i sink(int) internal sink current for blanking pulses; pll1 locked 1.4 2.0 2.6 ma i l(max) maximum external load current v hunlock =1v --- 2ma i l leakage current v hunlock = 5 v in case of unlocked pll1 and/or protection active -- 5 m a pll1 phase comparator and frequency-locked loop: pins hpll1 and hbuf t w(hsync)(max) maximum width of horizontal sync pulse (referenced to line period) -- 25 % t lock(hpll1) total lock-in time of pll1 - 40 80 ms i ctrl(hpll1) control currents notes 4 and 5 locked mode, level 1 - 15 -m a locked mode, level 2 - 145 -m a v hbuf buffered f/v voltage at hbuf (pin 27) minimum horizontal frequency - 2.5 - v maximum horizontal frequency - 0.5 - v symbol parameter conditions min. typ. max. unit
1999 jul 13 19 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 phase adjustments and corrections via pll1 and pll2 hpos horizontal position (referenced to horizontal period) register hpos = 0 -- 13 - % register hpos = 127 - 0 - % register hpos = 255 - 13 - % hpinbal horizontal pin unbalance correction via hpll2 (referenced to horizontal period) register hpinbal = 0; control bit hpc = 0; note 6 -- 0.8 - % register hpinbal = 15; control bit hpc = 0; note 6 - 0.8 - % register hpinbal = x; control bit hpc = 1; note 6 - 0 - % hparal horizontal parallelogram correction (referenced to horizontal period) register hparal = 0; control bit hbc = 0; note 6 -- 0.8 - % register hparal = 15; control bit hbc = 0; note 6 - 0.8 - % register hparal = x; control bit hbc = 1; note 6 - 0 - % hmoire relative modulation of horizontal position by 0.5f h ; phase alternates with 0.5f v register hmoire = 0; control bit mod = 0 - 0 - % register hmoire = 31; control bit mod = 0 - 0.05 - % hmoire off moire cancellation off control bit mod = 1 - 0 - % pll2 phase detector: pins hflb and hpll2 f pll2 pll2 control (advance of horizontal drive with respect to middle of horizontal ?yback) maximum advance; register hpinbal = 07; register hparal = 07 36 -- % minimum advance; register hpinbal = 07; register hparal = 07 - 7 - % i ctrl(pll2) pll2 control current - 75 -m a f pll2 relative sensitivity of pll2 phase shift related to horizontal period - 28 - mv/% v prot(pll2)(max) maximum voltage for pll2 protection mode/soft start - 4.4 - v i ch(pll2) charge current for external capacitor during soft start v hpll2 < 3.7 v - 1 -m a h orizontal flyback input : pin hflb v pos(hflb) positive clamping voltage i hflb =5ma - 5.5 - v v neg(hflb) negative clamping voltage i hflb = - 1ma -- 0.75 - v i pos(hflb) positive clamping current -- 6ma i neg(hflb) negative clamping current --- 2ma v sl(hflb) slicing level - 2.8 - v symbol parameter conditions min. typ. max. unit
1999 jul 13 20 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 output stage for line driver pulses: pin hdrv o pen - collector output stage v sat(hdrv) saturation voltage i hdrv =20ma -- 0.3 v i hdrv =60ma -- 0.8 v i lo(hdrv) output leakage current v hdrv =16v -- 10 m a a utomatic variation of duty cycle t hdrv(off) /t h relative t off time of hdrv output; measured at v hdrv = 3 v; hdrv duty cycle is modulated by the relation i href /i vref i hdrv = 20 ma; f h = 31.45 khz; see fig.16 42 45 48 % i hdrv = 20 ma; f h = 58 khz; see fig.16 45.5 48.5 51.5 % i hdrv = 20 ma; f h = 110 khz; see fig.16 49 52 55 % x-ray protection: pins xray and xsel v xray(sl) slicing voltage level for latch 6.22 6.39 6.56 v t w(xray)(min) minimum width of trigger pulse -- 30 m s r i(xray) input resistance at pin 2 v xray <6.38v+v be 500 -- k w v xray >6.38v+v be - 5 - k w standby mode - 5 - k w xray rst reset of x-ray latch pin 9 open-circuit or connected to gnd set control bit softst via the i 2 c-bus - pin 9 connected to v cc via r xsel switch off v cc then re-apply v cc - v cc(xray)(min) minimum supply voltage for correct function of the x-ray latch pin 9 connected to v cc via r xsel -- 4v v cc(xray)(max) maximum supply voltage for reset of the x-ray latch pin 9 connected to v cc via r xsel 2 -- v r xsel external resistor at pin 9 no reset via i 2 c-bus 56 - 130 k w vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f fr(v) ] f fr(v) free-running frequency r vref =22k w ; c vcap = 100 nf 40 42 43.3 hz f cr(v) vertical frequency catching range constant amplitude; note 7 50 - 160 hz v vref voltage at reference input for vertical oscillator - 3.0 - v t d(scan) delay between trigger pulse and start of ramp at vcap (pin 24) (width of vertical blanking pulse) control bit vblk = 0 220 260 300 m s control bit vblk = 1 305 350 395 m s i vagc amplitude control current control bit agcdis = 0 120 200 300 m a control bit agcdis = 1 - 0 -m a symbol parameter conditions min. typ. max. unit
1999 jul 13 21 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 c vagc external capacitor at vagc (pin 22) 150 - 220 nf differential vertical current outputs a djustment of vertical size including vga and eht compensation ; see fig.5 vsize vertical size without vga overscan (referenced to nominal vertical size) register vsize = 0; bit vovscn = 0; note 8 - 60 - % register vsize = 127; bit vovscn = 0; note 8 - 100 - % vsize vga vertical size with vga overscan (referenced to nominal vertical size) register vsize = 0; bit vovscn = 1; note 8 - 70 - % register vsize = 127; bit vovscn = 1; note 8 115.9 116.8 117.7 % vsmod eht eht compensation on vertical size via vsmod (pin 21) (referenced to 100% vertical size) i vsmod =0 - 0 - % i vsmod = - 120 m a -- 7 - % i i(vsmod) input current (pin 21) vsmod = 0 - 0 -m a vsmod = - 7% -- 120 -m a r i(vsmod) input resistance 300 - 500 w v ref(vsmod) reference voltage at input - 5.0 - v f ro(vsmod) roll-off frequency ( - 3 db) i vsmod = - 60 m a +15 m a (rms) 1 -- mhz a djustment of vertical position ; see fig.6 vpos vertical position (referenced to 100% vertical size) register vpos = 0; control bit vpc = 0 -- 11.5 - % register vpos = 127; control bit vpc = 0 - 11.5 - % register vpos = x; control bit vpc = 1 - 0 - % a djustment of vertical linearity ; see fig.7 vlin vertical linearity (s-correction) register vlin = 0; control bit vsc = 0; note 8 - 2 - % register vlin = 15; control bit vsc = 0; note 8 - 46 - % register vlin = x; control bit vsc = 1; note 8 - 0 - % d vlin symmetry error of s-correction maximum vlin -- 0.7 % symbol parameter conditions min. typ. max. unit
1999 jul 13 22 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 a djustment of vertical linearity balance ; see fig.8 vlinbal vertical linearity balance (referenced to 100% vertical size) register vlinbal = 0; control bit vlc = 0; note 8 - 3.3 - 2.5 - 1.7 % register vlinbal = 15; control bit vlc = 0; note 8 1.7 2.5 3.3 % register vlinbal = x; control bit vlc = 1; note 8 - 0 - % vmoire modulation of vertical picture position by 1 2 vertical frequency (related to 100% vertical size) register vmoire = 0; control bit mod = 0 - 0 - % register vmoire = 31; control bit mod = 0 - 0.08 - % moire cancellation off control bit mod = 1 - 0 - % vertical output stage: pins vout1 and vout2; see fig.29 d i vout(nom)(p-p) nominal differential output current (peak-to-peak value) d i vout =i vout1 - i vout2 ; nominal settings; note 8 0.76 0.85 0.94 ma i o(vout)(max) maximum output current at pins vout1 and vout2 control bit vovscn = 1 0.54 0.6 0.66 ma v vout allowed voltage at outputs 0 - 4.2 v d i os(vert)(max) maximum offset error of vertical output currents nominal settings; note 8 -- 2.5 % d i lin(vert)(max) maximum linearity error of vertical output currents nominal settings; note 8 -- 1.5 % ew drive output ew drive output stage : pin ewdrv; see figs 9 to 12 v const(ewdrv) bottom output voltage at pin ewdrv (internally stabilized) register hpin = 0; register hcor = 04; register htrap = 08; register hsize = 255 1.05 1.2 1.35 v v o(ewdrv)(max) maximum output voltage note 9 7.0 -- v i l(ewdrv ) load current -- 2ma tc ewdrv temperature coef?cient of output signal -- 600 10 - 6 /k v hpin(ewdrv) horizontal pincushion voltage register hpin = 0; note 8 - 0.04 - v register hpin = 63; note 8 - 1.42 - v v hcor(ewdrv) horizontal corner correction voltage register hcor = 0; control bit vsc = 0; note 8 - 0.08 - v register hcor = 31; control bit vsc = 0; note 8 -- 0.64 - v register hcor = x; control bit vsc = 1; note 8 - 0 - v symbol parameter conditions min. typ. max. unit
1999 jul 13 23 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 v htrap(ewdrv) horizontal trapezium correction voltage register htrap = 15; control bit vpc = 0; note 8 -- 0.33 - v register htrap = 0; control bit vpc = 0; note 8 - 0.33 - v register htrap = x; control bit vpc = 1; note 8 - 0 - v v hsize(ewdrv) horizontal size voltage register hsize = 255; note 8 - 0.13 - v register hsize = 0; note 8 - 3.6 - v v heht(ewdrv) eht compensation on horizontal size via hsmod (pin 31) i hsmod = 0; note 8 - 0.69 - v i hsmod = - 120 m a; note 8 - 0.02 - v i i(hsmod) input current (pin 31) v heht = 0.02 v - 0 -m a v heht = 0.69 v -- 120 -m a r i(hsmod) input resistance 300 - 500 w v ref(hsmod) reference voltage at input i hsmod =0 - 5.0 - v f ro(hsmod) roll-off frequency ( - 3 db) i hsmod = - 60 m a +15 m a (rms) 1 -- mhz t racking of ewdrv output signal with horizontal frequency proportional voltage f h(multi) horizontal frequency range for tracking 15 - 80 khz v par(ewdrv) parabola amplitude at ewdrv (pin 11) i href = 1.052 ma; f h = 31.45 khz; control bit fhmult = 1; note 10 - 0.72 - v i href = 2.341 ma; f h = 70 khz; control bit fhmult = 1; note 10 - 1.42 - v function disabled; control bit fhmult = 0; note 10 - 1.42 - v le ewdrv linearity error of horizontal frequency tracking -- 8% output for asymmetric ew corrections: pin ascor v hparal(ascor) vertical sawtooth voltage for ew parallelogram correction register hparal = 0; control bit hpc = 0; note 8 -- 0.825 - v register hparal = 15; control bit hpc = 0; note 8 - 0.825 - v register hparal = x; control bit hpc = 1; note 8 - 0.05 - v symbol parameter conditions min. typ. max. unit
1999 jul 13 24 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 v hpinbal(ascor) vertical parabola voltage for pin unbalance correction register hpinbal = 0; control bit hbc = 0; note 8 -- 1.0 - v register hpinbal = 15; control bit hbc = 0; note 8 - 1.0 - v register hpinbal = x; control bit hbc = 1; note 8 - 0.05 - v v o(ascor)(max)(p-p) maximum output voltage swing (peak-to-peak value) - 4 - v v o(ascor)(max) maximum output voltage - 6.5 - v v c(ascor) centre voltage - 4.0 - v v o(ascor)(min) minimum output voltage - 1.9 - v i o(ascor)(max) maximum output current v ascor 3 1.9 v -- 1.5 - ma i o(sink)(ascor)(max) maximum output sink current v ascor 3 1.9 v - 50 -m a focus section: pin focus; tda4854 only v hfocus(p-p) amplitude of horizontal parabola (peak-to-peak value) register hfocus = 0 - 0.06 - v register hfocus = 31 - 3.2 - v t precor pre-correction of phase 1.9 m s 1999 jul 13 25 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 c bop(min) minimum value of capacitor at pin 3 10 -- nf v oltage comparator : pin bsens v i(bsens) voltage range of positive comparator input 0 - 5v v i(bop) voltage range of negative comparator input 0 - 5v i l(bsens)(max) maximum leakage current discharge disabled --- 2 m a o pen - collector output stage : pin bdrv i o(bdrv)(max) maximum output current 20 -- ma i lo(bdrv) output leakage current v bdrv =16v -- 3 m a v sat(bdrv) saturation voltage i bdrv <20ma -- 300 mv t off(bdrv)(min) minimum off-time - 250 - ns t d(bdrv-hdrv) delay between bdrv pulse and hdrv pulse measured at v hdrv =v bdrv =3v - 500 - ns bsens discharge circuit : pin bsens v stop(bsens) discharge stop level capacitive load; i bsens = 0.5 ma 0.85 1.0 1.15 v i dch(bsens) discharge current v bsens > 2.5 v 4.5 6.0 7.5 ma v th(bsens)(restart) threshold voltage for restart fault condition 1.2 1.3 1.4 v c bsens(min) minimum value of capacitor at bsens (pin 4) 2 -- nf internal reference, supply voltage, soft start and protection v cc(stab) external supply voltage for complete stabilization of all internal references 9.2 - 16 v i cc supply current - 70 - ma i cc(stb) standby supply current stdby = 1; v pll2 <1v; 3.5 v < v cc <16v - 9 - ma psrr power supply rejection ratio of internal supply voltage f = 1 khz 50 -- db v cc(blank) supply voltage level for activation of continuous blanking v cc decreasing from 12 v 8.2 8.6 9.0 v v cc(blank)(min) minimum supply voltage level for function of continuous blanking v cc decreasing from 12 v 2.5 3.5 4.0 v v on(vcc) supply voltage level for activation of hdrv, bdrv, vout1, vout2 and hunlock v cc increasing from below typical 8 v 7.9 8.3 8.7 v symbol parameter conditions min. typ. max. unit
1999 jul 13 26 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 notes 1. for duration of vertical blanking pulse see subheading vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f fr(v) ]. 2. continuous blanking at clbl (pin 16) will be activated, if one of the following conditions is true: a) no horizontal flyback pulses at hflb (pin 1) within a line b) x-ray protection is triggered c) voltage at hpll2 (pin 30) is low during soft start d) supply voltage at v cc (pin 10) is low e) pll1 unlocked while frequency-locked loop is in search mode. 3. oscillator frequency is f min when no sync input signal is present (continuous blanking at pins 16 and 17). 4. loading of hpll1 (pin 26) is not allowed. 5. voltage at hpll1 (pin 26) is fed to hbuf (pin 27) via a buffer. disturbances caused by horizontal sync are removed by an internal sample-and-hold circuit. 6. all vertical and ew adjustments in accordance with note 8, but vsize = 80% (register vsize = 63 and control bit vovscn = 0). 7. value of resistor at vref (pin 23) may not be changed. 8. all vertical and ew adjustments are specified at nominal vertical settings; unless otherwise specified, which means: a) vsize = 100% (register vsize = 127 and control bit vovscn = 0) b) vsmod = 0 (no eht compensation) v off(vcc) supply voltage level for deactivation of bdrv, vout1, vout2 and hunlock; also sets register softst v cc decreasing from above typical 8.3 v 7.7 8.1 8.5 v t hresholds derived from hpll2 voltage v hpll2(blank)(ul) upper limit voltage for continuous blanking - 4.7 - v v hpll2(bduty)(ul) upper limit voltage for variation of bdrv duty cycle - 3.4 - v v hpll2(bduty)(ll) lower limit voltage for variation of bdrv duty cycle - 2.8 - v v hpll2(hduty)(ul) upper limit voltage for variation of hdrv duty cycle - 2.8 - v v hpll2(hduty)(ll) lower limit voltage for variation of hdrv duty cycle - 1.7 - v v hpll2(stby)(ll) lower limit voltage for vout1 and vout2 to be active via i 2 c-bus soft start - 1.1 - v v hpll2(stby)(ul) upper limit voltage for standby voltage - 1 - v v hpll2(stby)(ll) lower limit voltage for vout1 and vout2 to be active via external dc current - 0 - v symbol parameter conditions min. typ. max. unit
1999 jul 13 27 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 c) vpos centred (register vpos = x and control bit vpc = 1) d) vlin = 0 (register vlin = x and control bit vsc = 1) e) vlinbal = 0 (register vlinbal = x and control bit vlc = 1) f) fhmult = 0 g) hparal = 0 (register hparal = x and control bit hpc = 1) h) hpinbal = 0 (register hpinbal = x and control bit hbc = 1) i) vertical oscillator synchronized j) hsize = 255. 9. the output signal at ewdrv (pin 11) may consist of horizontal pincushion + corner correction + dc shift + trapezium correction. if the control bit vovscn is set, and the vpos adjustment is set to an extreme value, the tip of the parabola may be clipped at the upper limit of the ewdrv output voltage range. the waveform of corner correction will clip if the vertical sawtooth adjustment exceeds 110% of the nominal setting. 10. if f h tracking is enabled, the amplitude of the complete ewdrv output signal (horizontal pincushion + corner correction + dc shift + trapezium) will be changed proportional to i href . the ewdrv low level of 1.2 v remains fixed. 11. first pole of transconductance amplifier is 5 mhz without external capacitor (will become the second pole, if the ota operates as an integrator). 12. open-loop gain is at f = 0 with no resistive load and c bop = 10 nf [from bop (pin 3) to gnd]. v bop v bin ------------- - vertical and ew adjustments fig.5 adjustment of vertical size. (1) d i 1 is the maximum amplitude setting at register vsize = 127, control bit vovscn = 0, control bit vpc = 1, control bit vsc = 1 and control bit vlc = 1. vsize i d 2 i d 1 ------- - 100% = vsmod i d 2 i d 1 ------- - 100% = handbook, halfpage t i vout1 i vout2 d l 2 d l 1 (1) mbg590 fig.6 adjustment of vertical position. (1) d i 1 is the maximum amplitude setting at register vsize = 127 and control bit vpc = 1. vpos i 2 d i 1 d C 2i 1 d --------------------- - 100% = handbook, halfpage t i vout1 i vout2 d l 2 d l 1 (1) mbg592
1999 jul 13 28 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 fig.7 adjustment of vertical linearity (vertical s-correction). (1) d i 1 is the maximum amplitude setting at register vsize = 127 and vlin = 0%. vlin i d 1 i d 2 C i 1 d --------------------- - 100% = handbook, halfpage t i vout1 i vout2 d l 2 /d t d l 1 (1) /d t mbg594 fig.8 adjustment of vertical linearity balance. (1) d i 1 is the maximum amplitude setting at register vsize = 127, register vovscn = 0, control bit vpc = 1, control bit vlin = 1 and control bit vlinbal = 0. vlinbal i d 1 i d 2 C 2i 1 d --------------------- - 100% = handbook, halfpage t i vout1 i vout2 d i 1 (1) d i 2 mgm068 fig.9 adjustment of parabola amplitude at pin ewdrv. handbook, halfpage t v ewdrv v hpin(ewdrv) mgm069 fig.10 influence of corner correction at pin ewdrv. handbook, halfpage t v ewdrv v hcor(ewdrv) mgm070
1999 jul 13 29 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 fig.11 influence of trapezium at pin ewdrv. handbook, halfpage t v ewdrv v htrap(ewdrv) mgm071 fig.12 influence of hsize and eht compensation at pin ewdrv. handbook, halfpage t v ewdrv v hsize(ewdrv) + v heht(ewdrv) mgm072 fig.13 adjustment of parallelogram at pin ascor. handbook, halfpage t v hparal(ascor) mgm073 v ascor v c(ascor) fig.14 adjustment of pin balance at pin ascor. handbook, halfpage t v ascor v hpinbal(ascor) mgm074 v c(ascor)
1999 jul 13 30 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 pulse diagrams handbook, full pagewidth internal trigger inhibit window (typical 4 ms) 1.4 v 3.8 v automatic trigger level vertical sync pulse 4.0 v differential output currents vout1 (pin 13) and vout2 (pin 12) inhibited vertical oscillator sawtooth at vcap (pin 24) vertical blanking pulse at clbl (pin 16) vertical blanking pulse at hunlock (pin 17) synchronized trigger level ew drive waveform at ewdrv (pin 11) dc shift 3.6 v maximum 7.0 v maximum low-level 1.2 v fixed i vout1 i vout2 mgm075 fig.15 pulse diagram for vertical part.
1999 jul 13 31 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 handbook, full pagewidth + - + horizontal sync pulse pll2 control current at hpll2 (pin 30) pll1 control current at hpll1 (pin 26) line flyback pulse at hflb (pin 1) horizontal oscillator sawtooth at hcap (pin 29) line drive pulse at hdrv (pin 8) triggered on trailing edge of horizontal sync video clamping pulse at clbl (pin 16) vertical blanking level horizontal focus parabola at focus (pin 32) pll2 control range 45 to 52% of line period t precor mgm076 fig.16 pulse diagram for horizontal part.
1999 jul 13 32 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 handbook, full pagewidth relative t hdrv(off) /t h (%) mgm077 52 45 15 30 110 130 f h (khz) fig.17 relative t off time of hdrv as a function of horizontal frequency. handbook, full pagewidth composite sync (ttl) at hsync (pin 15) clamping and blanking pulses at clbl (pin 16) mbg596 fig.18 pulse diagrams for composite sync applications. a. reduced influence of vertical sync on horizontal phase. b. generation of video clamping pulses during vertical sync with serration pulses. handbook, full pagewidth composite sync (ttl) internal integration of composite sync internal vertical trigger pulse pll1 control voltage at hpll1 (pin 26) at hsync (pin 15) pulses at clbl (pin 16) clamping and blanking mgc947
1999 jul 13 33 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 i 2 c-bus protocol i 2 c-bus data format notes 1. s = start condition. 2. slave address (mad) = 1000 1100. 3. a = acknowledge, generated by the slave. no acknowledge, if the supply voltage is below 8.3 v for start-up and 8.1 v for shut-down procedure. 4. subaddress (sad). 5. data, if more than 1 byte of data is transmitted, then no auto-increment of the significant subaddress is performed. 6. p = stop condition. it should be noted that clock pulses according to the 400 khz specification are accepted for 3.3 and 5 v applications (reference level = 1.8 v). default register values after power-up are random. all registers have to be preset via software before the soft start is enabled. important : if the register contents are changed during the vertical scan, this might result in a visible interference on the screen. the cause for this interference is the abrupt change in picture geometry which takes effect at random locations within the visible picture. to avoid this kind of interference, the adjustment of the critical geometry parameters hsize, hpos, vsize and vpos should be synchronized with the vertical flyback. this should be done in such a way that the adjustment change takes effect during the vertical blanking time (see fig.19). for very slow i 2 c-bus interfaces, it might be necessary to delay the transmission of the last byte (or only the last bit) of an i 2 c-bus message until the start of the vertical sync or vertical blanking. s (1) slave address (2) a (3) subaddress (4) a (3) data (5) a (3) p (6) fig.19 timing of the i 2 c-bus transmission for interference-free adjustment. handbook, full pagewidth mgm088 vertical sync pulse vertical blanking pulse sda parameter change takes effect
1999 jul 13 34 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 table 4 list of i 2 c-bus controlled switches; notes 1 and 2 notes 1. x = dont care. 2. # = this bit is occupied by another function. if the register is addressed, the bit values for both functions must be transferred. 3. bits stdby and softst can be reset by internal protection circuit. control bit function sad (hex) register assignment d7 d6 d5 d4 d3 d2 d1 d0 blkdis 0: vertical, protection and horizontal unlock blanking available on pins clbl and hunlock 01x######d0 1: only vertical and protection blanking available on pins clbl and hunlock hbc 0: hpinbal (parabola) waveform enabled 01 x #####d1# 1: hpinbal (parabola) waveform disabled hpc 0: hparal (sawtooth) waveform enabled 01 x ####d2## 1: hparal (sawtooth) waveform disabled agcdis 0: agc in vertical oscillator active 01 x ###d3### 1: agc in vertical oscillator inhibited vsc 0: vlin and hcor adjustments enabled 01 x # # d4 #### 1: vlin and hcor adjustments forced to centre value mod 0: horizontal and vertical moire cancellation enabled 01 x # d5 ##### 1: horizontal and vertical moire cancellation disabled tvmod 0: tv mode at f min not activated 01 x d6 ###### 1: tv mode at f min activated fhmult 0: ew output independent of horizontal frequency 0b ######xd0 1: ew output tracks with horizontal frequency vovscn 0: vertical size 100% 0b #####d2x# 1: vertical size 116.8% for vga350 clamp 0: trailing edge for horizontal clamp 0b ####d3#x# 1: leading edge for horizontal clamp vblk 0: vertical blanking = 260 m s 0b###d4##x# 1: vertical blanking = 340 m s vlc 0: vlinbal adjustment enabled 0b # # d5 ###x# 1: vlinbal adjustment forced to centre value vpc 0: vpos and htrap adjustments enabled 0b # d6 ####x# 1: vpos and htrap adjustments forced to centre value acd 0: ascor disconnected from pll2 0b d7 #####x# 1: ascor internally connected with pll2 stdby (3) 0: internal power supply enabled 0d xxxxxx# d0 1: internal power supply disabled softst (3) 0: soft start not released (pin hpll2 pulled to ground) 0d xxxxxxd1# 1: soft start is released (power-up via pin hpll2)
1999 jul 13 35 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 5 list of i 2 c-bus controlled functions and those accessible by pins; notes 1 and 2 function name bits sad (hex) register assignment control bit range function tracks with d7 d6 d5 d4 d3 d2 d1 d0 horizontal size hsize 8 00 d7 d6 d5 d4 d3 d2 d1 d0 - 0.1 to 3.6 v hsmod vertical position vpos 7 02 d7 d6 d5 d4 d3 d2 d1 x vpc 11.5% vsmod vertical linearity balance vlinbal 4 03 x d6 d5 d4 d3 # # # vlc 2.5% of 100% vertical size vsize, vovscn, vpos and vsmod moire cancellation via vertical position vmoire 3 03 # # # # # d2 d1 d0 mod 0 to 0.08% of vertical amplitude - horizontal pincushion hpin 6 04 x x d5 d4 d3 d2 d1 d0 - 0 to 1.44 v vsize, vovscn, vpos, hsize and hsmod moire cancellation via horizontal position hmoire 5 05 x x x d4 d3 d2 d1 d0 mod 0 to 0.05% of horizontal period - horizontal position hpos 8 06 d7 d6 d5 d4 d3 d2 d1 d0 - 13% of horizontal period - vertical linearity vlin 4 07 d7 d6 d5 d4 # # # # vsc - 2to - 46% vsize, vovscn, vpos and vsmod ew pin balance hpinbal 4 07 # # # # d3 d2 d1 d0 hbc and acd 1% of horizontal period vsize, vovscn and vpos vertical size vsize 7 08 d7 d6 d5 d4 d3 d2 d1 x - 60 to 100% vsmod horizontal corner correction hcor 5 09 x x x d4 d3 d2 d1 d0 vsc +6 to - 46% of parabola amplitude vsize, vovscn, vpos, hsize and hsmod horizontal trapezium correction htrap 4 0c d7 d6 d5 d4 # # # # vpc 0.33 v vsize, vovscn, vpos, hsize and hsmod horizontal parallelogram hparal 4 0c # # # # d3 d2 d1 d0 hpc and acd 1% of horizontal period vsize, vovscn and vpos
1999 jul 13 36 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... notes 1. x = dont care. 2. # = this bit is occupied by another function. if the register is addressed, the bit values for both functions must be transferr ed. tda4854 vertical focus vfocus 3 0a d7 d6 d5 # # # # # - 0 to 25% vsize, vovscn and vpos horizontal focus hfocus 5 0a # # # d4 d3 d2 d1 d0 - 0 to 100% - function name bits sad (hex) register assignment control bit range function tracks with d7 d6 d5 d4 d3 d2 d1 d0
1999 jul 13 37 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 start-up procedure v cc < 8.3 v: as long as the supply voltage is too low for correct operation, the ic will give no acknowledge due to internal power-on reset (por) supply current is 9 ma or less. v cc > 8.3 v: the internal por has ended and the ic is in standby mode control bits stdby and softst are reset to their start values all other register contents are random pin hunlock is at high-level. setting control bit stdby = 0: enables internal power supply supply current increases from 9 to 70 ma when v cc < 8.6 v register softst cannot be set by the i 2 c-bus output stages are disabled, except the vertical output pin hunlock is at high-level. setting all registers to defined values: due to the hardware configuration of the ic (no auto-increment) any register setting needs a complete 3-byte i 2 c-bus data transfer as follows: start - ic address - subaddress - data - stop. setting control bit softst = 1: before starting the soft-start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive hdrv duty cycle increases bdrv duty cycle increases pll1 and pll2 are enabled. ic in full operation: pin hunlock is at low-level when pll1 is locked any change of the register content will result in immediate change of the output behaviour setting control bit softst = 0 is the only way (except power-down via pin v cc ) to leave the operating mode. soft-down sequence: see l4 of fig.21 for starting the soft-down sequence. fig.20 i 2 c-bus flow for start-up. (1) see fig.21. mgm078 start standby mode (xxxx xx01) stdby = 1 softst = 0 all other register contents are random protection mode (xxxx xx00) stdby = 0 softst = 0 all other register contents are random protection mode (xxxx xx00) stdby = 0 softst = 0 registers are pre-set change/refresh of data? s 8ch a 0dh a 00h a p s 8ch a 0dh a 02h a p s 8ch a sad a data a p s 8ch a sad a data a p operating mode (xxxx xx10) stdby = 0 softst = 1 soft-start sequence (xxxx xx10) stdby = 0 softst = 1 power-down mode (xxxx xxxx) no acknowledge is given by ic all register contents are random l1 l2 l3 l4 (1) v cc > 8.3 v no yes softst = 0? no yes all registers defined? no yes
1999 jul 13 38 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 protection and standby mode soft-down sequence: start the sequence by setting control bit softst = 0 bdrv duty cycle decreases hdrv duty cycle decreases. protection mode: pins hdrv and bdrv are floating continuous blanking at pin clbl is active pin hunlock is floating pll1 and pll2 are disabled register contents are kept in internal memory. protection mode can be left by 3 ways: 1. entering standby mode by setting control bit softst = 0 and control bit stdby = 1 2. starting the soft-start sequence by setting control bit softst = 1 (bit stdby = dont care); see l3 of fig.20 for continuation 3. decreasing the supply voltage below 8.1 v. standby mode: set control bit stdby = 1 driver outputs are floating (same as protection mode) supply current is 9 ma only the i 2 c-bus and protection circuits are operative contents of all registers except the value of bit stdby and bit softst are lost see l2 of fig.20 for continuation. mbk382 standby mode (xxxx xx01) stdby = 1 softst = 0 all other register contents are random soft-down sequence (xxxx xx00) stdby = 0 softst = 0 l4 l3 (1) no yes softst = 1? yes l2 (1) protection mode (xxxx xx00) stdby = 0 softst = 0 registers are set no stdby = 1? s 8ch a 0dh a 00h a p s 8ch a 0dh a 01h a p fig.21 i 2 c-bus flow for protection and standby mode. (1) see fig.20.
1999 jul 13 39 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 handbook, full pagewidth mgm079 ( any mode) power-down mode no acknowledge is given by ic all register contents are random l1 (1) v cc < 8.1 v v cc a soft-down sequency followed by a soft start sequence is generated internally. 8.6 v 8.1 v v cc ic enters standby mode. 8.6 v 8.1 v fig.22 i 2 c-bus flow for any mode. (1) see fig.20. power-down mode power dip of v cc < 8.6 v: the soft-down sequence is started first. then the soft-start sequence is generated internally. power dip of v cc < 8.1 v or v cc shut-down: this function is independent from the operating mode, so it works under any condition. all driver outputs are immediately disabled ic enters standby mode.
1999 jul 13 40 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 application information fig.23 application and timing for feedback mode. for f < 50 khz and c2 < 47 nf calculation formulas and behaviour of the ota are the same as for an op. an exception is the limited output current at bop (pin 3). see chapter characteristics, row head b+ control section; see figs 23 and 24. (1) the recommended value for r6 is 1 k w . a. feedback mode application. b. waveforms for normal operation. c. waveforms for fault condition. handbook, full pagewidth v hdrv v bsens v bsens = v bop v bdrv t off(min) t on horizontal flyback pulse v restart(bsens) v stop(bsens) 2 3 4 1 mbg600 t d(bdrv) handbook, full pagewidth soft start s r q q horizontal output stage v hdrv v cc v i 6 d2 tr1 r5 c4 r4 r6 (1) l ota 2.5 v v hpll2 5 v bin v bop v bsens v bdrv c bop d1 r1 r3 ewdrv c1 r2 c2 34 > 10 nf horizontal flyback pulse inverting buffer 3 2 4 1 mgm080 discharge
1999 jul 13 41 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 fig.24 application and timing for feed forward mode. a. forward mode application. b. waveforms for normal operation. c. waveforms for fault condition. handbook, full pagewidth v bop v bop v stop(bsens) t off v restart(bsens) v hdrv v bsens v bdrv horizontal flyback pulse 2 3 4 i mosfet 5 1 t on (discharge time of c bsens ) mbg602 t d(bdrv) soft start s r q q v hdrv v cc 6 r4 (1) ota 2.5 v v hpll2 5 v bop v bsens v bdrv 34 inverting buffer 3 2 4 discharge horizontal output stage d2 tr1 r3 v bin c bsens c bop r1 r2 c1 d1 tr2 > 10 nf > 2 nf horizontal flyback pulse 1 i mosfet 5 eht transformer eht adjustment power-down mgm081 (1) the recommended value for r4 is 1 k w .
1999 jul 13 42 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 start-up sequence and shut-down sequence fig.25 start-up sequence and shut-down sequence. a. start-up sequence. b. shut-down sequence. handbook, full pagewidth v cc continuous blanking off pll2 soft start/soft-down enabled (1) 8.6 v 3.5 v continuous blanking (pin 16 and 17) activated time 8.3 v data accepted from i 2 c-bus video clamping pulse enabled if control bit stdby = 0 mgm082 handbook, full pagewidth v cc mgm083 continuous blanking (pin 16 and 17) activated pll2 soft-down sequence is triggered (2) 8.6 v 8.1 v 3.5 v continuous blanking disappears time no data accepted from i 2 c-bus video clamping pulse disabled (1) see figs 20, 21, 22, 26 and 27. (2) see figs 26b and 27b.
1999 jul 13 43 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 pll2 soft start sequence and pll2 soft-down sequence fig.26 pll2 soft start sequence and pll2 soft-down sequence via the i 2 c-bus. a. pll2 soft start sequence, via the i 2 c-bus, if v cc > 8.6 v. b. pll2 soft-down sequence, via the i 2 c-bus, if v cc > 8.6 v. (1) hdrv, bdrv, vout2 and vout1 are floating for v cc < 8.6 v. handbook, full pagewidth v hpll2 continuous blanking off pll2 enabled frequency detector enabled hdrv/hflb protection enabled 4.7 v 3.4 v 1.7 v time hdrv duty cycle begins to increase 1 v vout1 and vout2 enabled bdrv duty cycle begins to increase hdrv duty cycle has reached nominal value 2.8 v bdrv duty cycle has reached nominal value duty cycle increases mgm084 handbook, full pagewidth v hpll2 continuous blanking (pin 16 and 17) activated pll2 disabled frequency detector disabled hdrv/hflb protection disabled 4.7 v 3.4 v 1.7 v time hdrv floating 1 v vout1 and vout2 floating bdrv duty cycle begins to decrease (1) 2.8 v bdrv floating hdrv duty cycle begins to decrease (1) duty cycle decreases mgm085
1999 jul 13 44 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 fig.27 pll2 soft start sequence and pll2 soft-down sequence by external dc current. a. pll2 soft start sequence by external dc current, if v cc > 8.6 v. b. pll2 soft-down sequence by external dc current, if v cc > 8.6 v. (1) hdrv, bdrv, vout2 and vout1 are floating for v cc < 8.6 v. handbook, full pagewidth v hpll2 continuous blanking off pll2 enabled frequency detector enabled hdrv/hflb protection enabled 4.6 v 3.3 v 1.7 v time hdrv duty cycle begins to increase bdrv duty cycle begins to increase hdrv duty cycle has reached nominal value 3.0 v bdrv duty cycle has reached nominal value duty cycle increases mhb108 handbook, full pagewidth v hpll2 continuous blanking (pin 16 and 17) activated pll2 disabled frequency detector disabled hdrv/hflb protection disabled 4.6 v 3.3 v 1.7 v time hdrv floating bdrv duty cycle begins to decrease (1) 3.0 v bdrv floating hdrv duty cycle begins to decrease (1) duty cycle decreases mhb109
1999 jul 13 45 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 handbook, full pagewidth mgm087 floating floating floating x-ray latch triggered v xray v hunlock bdrv duty cycle hdrv duty cycle vout1, vout2 approximately 25 ms fig.28 activation of the soft-down sequence via pin xray. vertical linearity error fig.29 definition of vertical linearity error. (1) i vout =i vout1 - i vout2 . (2) i 1 =i vout at v vcap = 1.9 v. (3) i 2 =i vout at v vcap = 2.6 v. (4) i 3 =i vout at v vcap = 3.3 v. which means: vertical linearity error = i 0 i 1 i 3 C 2 -------------- = 1 max i 1 i 2 C i 0 -------------- or i 2 i 3 C i 0 -------------- ? ?? C handbook, halfpage i 1 (2) i 2 (3) i 3 (4) i vout (1) ( m a) + 415 - 415 0 v vcap mbg551
1999 jul 13 46 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 printed-circuit board layout fig.30 hints for printed-circuit board (pcb) layout. handbook, full pagewidth tda4853; tda4854 1 2 3 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 external components of horizontal section external components of horizontal section b-drive line in parallel to ground 470 pf 2.2 nf 47 nf 100 m f 12 v external components of vertical section further connections to other components or ground paths are not allowed only this path may be connected to general ground of pcb for optimum performance of the tda4853; tda4854 the ground paths must be routed as shown. only one connection to other grounds on the pcb is allowed. note: the tracks for hdrv and bdrv should be kept separate. pin 25 should be the 'star point' for all small signal components no external ground tracks connected here mgm086 smd 4
1999 jul 13 47 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 internal pin configuration pin symbol internal circuit 1 hflb 2 xray 3 bop 4 bsens 1.5 k w 7 x 1 mbg561 5 k w 6.25 v 2 mbg562 5.3 v 3 mbg563 4 mbg564
1999 jul 13 48 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 5 bin 6 bdrv 7 pgnd power ground, connected to substrate 8 hdrv 9 xsel 10 v cc 11 ewdrv pin symbol internal circuit 5 mbg565 6 mbg566 8 mgm089 9 mbk381 4 k w 10 mgm090 108 w 108 w 11 mbg570
1999 jul 13 49 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 12 vout2 13 vout1 14 vsync 15 hsync 16 clbl pin symbol internal circuit 12 mbg571 13 mbg572 100 w 2 k w 14 7.3 v 1.4 v mbg573 85 w 15 1.4 v 1.28 v 7.3 v mbg574 16 mbg575
1999 jul 13 50 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 17 hunlock 18 scl 19 sda 20 ascor 21 vsmod pin symbol internal circuit 17 mgm091 18 mgm092 19 mgm093 20 480 w mgm094 21 250 w 5 v mgm095
1999 jul 13 51 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 22 vagc 23 vref 24 vcap 25 sgnd signal ground 26 hpll1 27 hbuf pin symbol internal circuit 22 mbg581 23 3 v mbg582 24 mbg583 26 4.3 v mgm096 27 mgm097 5 v
1999 jul 13 52 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 28 href 29 hcap 30 hpll2 31 hsmod pin symbol internal circuit 76 w 28 2.525 v 29 7.7 v mbg585 30 7.7 v 6.25 v hflb mgm098 31 250 w 5 v mgm099
1999 jul 13 53 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 note 1. this pin is internally connected for tda4853. 32 focus (1) pin symbol internal circuit 32 200 w 120 w 120 w mgm100 electrostatic discharge (esd) protection fig.31 esd protection for pins 4, 11 to 13, 16 and 17. pin mbg559 fig.32 esd protection for pins 2, 3, 5, 18 to 24 and 26 to 32. pin 7.3 v 7.3 v mbg560
1999 jul 13 54 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot232-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 32 1 17 16 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip32: plastic shrink dual in-line package; 32 leads (400 mil) sot232-1
1999 jul 13 55 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 soldering introduction to soldering through-hole mount packages this text gives a brief insight to wave, dip and manual soldering. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). wave soldering is the preferred method for mounting of through-hole mount ic packages on a printed-circuit board. soldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. suitability of through-hole mount ic packages for dipping and wave soldering methods note 1. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. package soldering method dipping wave dbs, dip, hdip, sdip, sil suitable suitable (1)
1999 jul 13 56 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 jul 13 57 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 notes
1999 jul 13 58 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 notes
1999 jul 13 59 philips semiconductors product speci?cation i 2 c-bus autosync de?ection controllers for pc/tv monitors tda4853; tda4854 notes
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go to philips semiconductors' home page select & go... start part catalog & datasheets catalog by function discrete semiconductors audio clocks and watches data communications microcontrollers peripherals standard analog video wired communications wireless communications catalog by system automotive consumer multimedia systems communications pc/pc-peripherals cross reference models packages application notes selection guides other technical documentation end of life information datahandbook system relevant links about catalog tree about search about this site subscribe to enews catalog & datasheets search tda4853; tda4854 tda4853; tda4854 information as of 2000 - 08 - 20 tda4853; tda4854; i2c - bus autosync deflection controllers for pc/tv monitors the tda4854 is a high performance and efficient solution for autosync monitors. all functions are controllable by i 2 c - bus. the tda4854 provides synchronization processing, horizontal and vertical synchronization with full autosync capability, a tv/vcr mode and very short settling times after mode changes. external power components are given a great deal of protection. the ic generates the drive waveforms for dc - coupled vertical boosters such as the tda486x and tda835x. the tda4854 provides extended functions e.g. as a flexible b+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals. the tda4853 is an economy version of the tda4854, especially designed for use in 14" and 15" monitors with combined eht generation. it provides the same features as the tda4854 except for the dynamic focus block. together with the i 2 c - bus driven philips tda488x video processor family, a very advanced system solution is offered. concept features l full horizontal plus vertical autosync capability; tv and vcr mode included l extended horizontal frequency range from 15 to 130 khz l comprehensive set of i 2 c - bus driven geometry adjustments and functions, including standby mode l very good vertical linearity l moire cancellation l start - up and switch - off sequence for safe operation of all power components l x - ray protection l flexible switched mode b+ supply function block for feedback and feed forward converter ? description ? features ? datasheet ? products, packages, availability and ordering ? find similar products to be kept informed on tda4853; tda4854, subscribe to enews. subscribe to enews description features
l internally stabilized voltage reference l drive signal for focus amplifiers with combined horizontal and vertical parabola waveforms (tda4854) l dc controllable inputs for extremely high tension (eht) compensation l sdip32 package. synchronization l can handle all sync signals (horizontal, vertical, composite and sync - on - video) l output for video clamping (leading/trailing edge selectable by i 2 c - bus), vertical blanking and protection blanking l output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube. horizontal section l i 2 c - bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase l frequency - locked loop for smooth catching of horizontal frequency l tv mode at 15.625 or 15.750 khz selectable by i 2 c - bus l simple frequency preset of f min and f max by external resistors l low jitter l soft start for horizontal and b+ control drive signals. vertical section l i 2 c - bus controllable vertical picture size, picture position, linearity (s - correction) and linearity balance l output for i 2 c - bus controllable vertical sawtooth and parabola (for pin unbalance and parallelogram) l vertical picture size independent of frequency l differential current outputs for dc coupling to vertical booster l 50 to 160 hz vertical autosync range. east - west (ew) section l i 2 c - bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction l optional tracking of ew drive waveform with line frequency selectable by i 2 c - bus. focus section of tda4854 l i 2 c - bus controllable output for horizontal and vertical parabolas l vertical parabola is independent of frequency and tracks with vertical adjustments l horizontal parabola independent of frequency l pre - correction of delay in focus output stage. datasheet
tda4853; tda4854 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. the similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. type nr. title publication release date datasheet status page count file size (kb) datasheet tda4853; tda4854 i2c-bus autosync deflection controllers for pc/tv monitors 13-jul-99 product specification 60 255 download products, packages, availability and ordering partnumber north american partnumber order code (12nc) marking/packing package device status buy online tda4853/v1 9352 374 60112 standard marking * tube sot232 development - tda4854/v2/s1 9352 611 55112 standard marking * tube sot232 full production - find similar products: copyright ? 2000 royal philips electronics all rights reserved. terms and conditions .

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